The present invention relates to an instruction fetch control method and, more particularly, to an instruction fetch method which involves efficiently fetching instructions from a memory and supplying the instructions to an instruction processor which processes a sequence of instructions in order to execute data processing.
Heretofore, instruction processors for data processors have adopted an instruction fetch control in which a plurality of instruction buffers are pre-fetched in order to accomplish instruction processing at a high speed. In the pre-fetch control for pre-fetching instructions, an instruction read request is provided to the memory (hereinafter also referred to as a first instruction fetch) whenever a portion of the instruction buffers is rendered empty as the instruction processing advances, in order to avoid rendering all of the instruction buffers empty. Further, processing performance, when a branch destination instruction read request is given to the plural instruction buffers in processing a branch instruction, when the branch instruction is decoded or when the appearance of a branch instruction is predicted from the processing history (this instruction fetch being hereinafter also referred to as a second instruction fetch; for example, as disclosed in Japanese Patent Unexamined Publication (kokai) No. 59-91,522/1984).
As disclosed in Japanese Patent Unexamined Publication (kokai) No. 62-77,648/1987, for example, for the instruction pre-fetch control of this kind, there is proposed a method which involves issuing an instruction read request to the memory regardless of whether the instruction buffer is in an empty state and accepting the instruction read request in fetching the fetched instruction into the instruction buffer when the instruction buffer is empty, while suppressing the acceptance of the instruction read request when the instruction buffer is not empty.
It is to be noted that, in order to always ensure an adequate quantity of instructions within the instruction buffers, for example, an instruction read request is required to be given whenever an empty capacity reaches eight bytes if the instruction buffer has the capacity of 32 bytes. Therefore, in this case, the quantity of instructions to be fetched upon one instruction read request becomes relatively small.
In the second instruction fetch, as all of the instruction buffers are rendered empty, it is necessary to immediately store the fetched instructions in the instruction buffers. Therefore, in this case, it is desired to fetch as many instructions as possible in one instruction read request.
For these reasons, in conventional pre-fetch control, the amount of instructions to be fetched per one instruction read request is controlled so as to adapt the quantity required for the second instruction fetch, with the impact upon the hardware amount and performance taken into consideration. Therefore, in implementing the first instruction fetch, only a fixed length from the top out of the fetched instruction is stored in the instruction buffer and the rest is left unemployed. For instance, suppose that, when the instruction buffer has the capacity of 32 bytes as in the previous case, 16 bytes of the instruction out of the 32 bytes are fetched by one request. In this case, in the second instruction fetch, the instruction read requests are issued twice, thereby filling the instruction buffer of 32 bytes with the instructions fetched, while in the first instruction fetch, the former 8 bytes out of the 16 bytes fetched are stored in the instruction buffer and the latter 8 bytes are left unemployed.
If a large number of instruction buffers are provided and a branch destination is fetched, a frequency of instruction read request increases as the number of instruction buffers increases. Further, in instances where a branch destination instruction is fetched by predicting the appearance of a branch instruction from the past history, the fetch timing becomes earlier, as compared with the fetching of the branch destination instructions when the branch instruction is decoded, thereby further increasing a frequency of the instruction read requests.
As described hereinabove, in the instruction fetch control in conventional technique, the frequency of the second instruction read request increases when the first instruction is fetched at a constant frequency, thereby causing collision between the instruction read requests. As a result, memory overhead increases, leading to a reduction in overall processing performance.